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st sitronix ST7065C 40ch segment/common driver for dot matrix lcd v1.4c 2009/08/21 1/14 functions: dot matrix lcd driver with two 20 channel outputs selectable function to use common/segment drivers simultaneously bias voltage (v1 ~ v6) input/output signals input : serial display data and control pulse from controller ic output : 20 x 2 channels waveform for lcd driving features: display driving bias : static to 1/5 power supply for logic : 2.7v ~ 5.5v power supply for lcd voltage (v dd ~v ee ) : 3v ~ 11v 64 pin qfp package and bare chip available description: ST7065C is a segment/common driver for dot matrix type lcd display. it features 40 channels with 20 x 2 bits bi-directional shift registers, da ta latches, lcd drivers and logic control circuits. it is fabricated by high voltage cmos process with low current consumption. the ST7065C can convert serial data received from a lcd controller, such as st7066u , into parallel data and send out lcd driving waveforms to the lcd panel. the ST7065C is designed for general-purpose lcd drivers. it can drive both static and dynamic drive lcd. the lsi can be used as segment/common driver. the ST7065C has pin function compatibility with the ks0065b that allows the user easily to replace it with a ST7065C .
ST7065C v1.4c 2009/08/21 2/14 ST7065C specification revision history version date description 1.1 2000/07/31 first edition 1.2 2000/11/14 added qfp pad configuration(page 4) 1.3 2001/04/18 moved qfp package dimensions(page 13) to page 4 change shift register table(page 8) 1.4 2001/05/04 st7065 transition to ST7065C 1.4a 2001/08/29 added substrate connect to vdd(page 3) 1.4b 2007/08/17 modify temperature range 1.4c 2009/08/21 added com/seg application circuit(page11 )
ST7065C v1.4c 2009/08/21 3/14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 size : 2310x1830mcoordinate : center min. pad pitch : 120m pad size : 85x90m (0,0) g798e "g798e" marking : easy to find the pad 59 58 57 56 55 54 53 52 51 50 49 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 31 20 21 22 23 24 25 26 27 28 29 30 substrate connect to vdd. functional block diagram pad arrangement segment driver segment driver bidirectional shifter(20bits) bidirectional shifter(20bits) data latch(20bits) data latch(20bits) contol v1v2 v3 v4 cl2 cl1 m dl1 shl1 dr1 dl2 shl2 dr2 v dd v ss v ee s1...............................s20 s21...............................s40 v5v6 fcs
ST7065C v1.4c 2009/08/21 4/14 package dimensions
ST7065C v1.4c 2009/08/21 5/14 pad configuration(qfp 64) nc s 34 s 33 s 32 s 31 s 30 nc s 35 s 36 s 37 s 38 s 39 s 40 s 09 s 10 s 11 s 08 s 07 vd d nc s 06 s 05 s 04 s 03 s 02 s 01 64 63 62 61 60 59 58 57 56 55 54 53 52 20 21 22 23 24 25 26 27 28 29 30 31 32 nc s29s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 v6v5 v4 v3 v2 v1 fcs shl2shl1 m nc dr2 dl2 dr1 dl1vss cl2cl1 vee 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 5150 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ST7065C v1.4c 2009/08/21 6/14 pad name and coordinates pad no. pad name x y pad no. pad name x y 1 vee -1045 -670 31 s[28] 1040 800 2 cl1 -1040 -805 32 s[27] 910 805 3 cl2 -910 -805 33 s[26] 780 805 4 vss -780 -805 34 s[25] 660 805 5 dl1 -660 -805 35 s[24] 540 805 6 dr1 -540 -805 36 s[23] 420 805 7 dl2 -420 -805 37 s[22] 300 805 8 dr2 -300 -805 38 s[21] 180 805 9 m -180 -805 39 s[20] 60 805 10 shl1 -60 -805 40 s[19] -60 805 11 shl2 60 -805 41 s[18] -180 805 12 fcs 180 -805 42 s[17] -300 805 13 v1 300 -805 43 s[16] -420 805 14 v2 420 -805 44 s[15] -540 805 15 v3 540 -805 45 s[14] -660 805 16 v4 660 -805 46 s[13] -780 805 17 v5 780 -805 47 s[12] -910 805 18 v6 910 -805 48 s[9] -1040 800 19 s[40] 1040 -800 49 s[10] -1045 670 20 s[39] 1045 -623 50 s[11] -1045 540 21 s[38] 1045 -488 51 s[8] -1045 420 22 s[37] 1045 -358 52 s[7] -1045 300 23 s[36] 1045 -233 53 vdd -1045 180 24 s[35] 1045 -108 54 s[6] -1045 60 25 s[30] 1045 20 55 s[5] -1045 -60 26 s[31] 1045 145 56 s[4] -1045 -180 27 s[32] 1045 270 57 s[3] -1045 -300 28 s[33] 1045 395 58 s[2] -1045 -420 29 s[34] 1045 525 59 s[1] -1045 -540 30 s[29] 1045 655
ST7065C v1.4c 2009/08/21 7/14 pin description: pin name purpose description i/o vdd power for logic n/a vss ground for logic n/a vee lcd gnd for lcd driving voltage n/a v1 v2 lcd output used as select voltage level i v3 v4 lcd output used as non select voltage level f or part i i v5 v6 lcd output used as non select voltage level f or part ii i s[1]-s[20] segment lcd driver output for part 1 o shl1 direction direction control for part 1 segment s i dl1, dr1 data in /out if shl1 = 1 then dl1=out, dr1=in if shl1 = 0 then dl1=in, dr1=out i/o s[21]-s[40] segment lcd driver output for part 2 o shl2 direction direction control for part 2 segment s i dl2, dr2 data in/out if shl2 = 1 then dl2=out, dr2=in if shl2 = 0 then dl2=in, dr2=out i/o m alternation alternate the lcd driving waveform i cl1 latch clock latch the data after shift is compl eted i cl2 shift clock shift the data into the segments i fcs mode selection mode select signal for part ii i
ST7065C v1.4c 2009/08/21 8/14 functional description: shift registers and data i/o the ST7065C supplies two sets of shift register, which control s the shift direction by shl1 & shl2. the dl1, dr1, dl2 and dr2 are data in put or output option function. shift direction of channel 1 shl1 shift direction dl1 dr1 0 s[1] s[20] in out 1 s[20] s[1] out in clock and mode selection in channel 1 part, the cl1 is the clock to latch da ta on the falling edge. it latches the data input from the bi-directional shift register a t the falling edge of cl1 and transfers its outputs to the lcd driver circuit. the cl2 is t he clock to shift data on the falling edge. it shifts the serial data at the falling of c l2 and transfers the output of each bit of the register to the latch circuit. in channel 2 part, the cl1 and cl2 is the clock to latch or shift data on the falling or rising edge which is depend on fcs value. when fcs is low, the channel 2 function is the same as channel 1 as a segment driver. when fcs is high, the channel 2 function will become a common driver. detail functi ons are show in the following table: fcs clock eage channel 1 channel 2 latch data latch data cl1 ---- ---- shift data shift data 0 cl2 ---- ---- latch data ---- cl1 ---- shift data shift data ---- 1 cl2 ---- latch data shift direction of channel 2 shl2 shift direction dl2 dr2 0 s[21] s[40] in out 1 s[40] s[21] out in
ST7065C v1.4c 2009/08/21 9/14 lcd output waveform the output levels of channel1 and channel2 are deci ded by the combination of fcs, m, and latched data. refer to the following table: fcs latched data m channel 1 channel 2 1 v1 v2 1 0 v2 v1 1 v3 v6 1 0 0 v4 v5 1 v1 v1 1 0 v2 v2 1 v3 v5 0 0 0 v4 v6 note: to use the same function of channel 1 and channel 2 as a segment driver, v3 and v5, v4 and v6 need to short respectively. output of latch data m channel1 output (s[1] ~ s[20]) v1 v1 v2 v3 v4 v2 v3 v4 fcs v2 v1 v6 v5 v1 v2 v5 v6 channel2 output (s[21] ~ s[40])
ST7065C v1.4c 2009/08/21 10/14 channel 1 used as a segment driver and channel 2 as a common driver (fcs=1) when channel 2 is used as a common driver, fcs is c onnected to vdd. channel 2 will shift data on the rising edge of cl1 and latch data on the rising edge of cl2. lcd controller d cl1 cl2 m flm dl1 cl1 cl2 m dl2 v1 v2 v3 v4 v5 v6 s[1] s[20] s[21] s[40] ST7065C fcs shl1 shl2 vdd vss to lcd segment to lcd common bias_v1 bias_v2 bias_v3 bias_v4 bias_v5 vcc(+5v) --- --- both channels 1 and 2 used as segment drivers (fcs= 0) when both channels 1 and 2 of the ST7065C are used as segment drivers, they will shift data on the falling edge of cl2 and latch dat a on the falling edge of cl1. v3&v5, v4&v6 are shorted in the application circuit as shown in the following figure. lcd controller d cl1 cl2 m dl1 cl1 cl2 m v1 v2 v3 v4 v5 v6 s[1] s[40] ST7065C fcs shl1 shl2 vss to lcd segment bias_v1 bias_v2 bias_v3 bias_v4 bias_v5 vcc(+5v) --- dr1 dl2
ST7065C v1.4c 2009/08/21 11/14 one ST7065C used as a common driver and the other s t7065c as a segment driver (fcs=0) the ST7065C are used as common drivers, the fcs is set low and the signals (cl1, cl2, m) from the controller are connected. v3&v5, v 4&v6 are shorted in the application circuit as shown in the following figur e. the other ST7065C are used as segment drivers, they will shift data on the falling edge of cl2 and latch data on the falling edge of c l1. v3&v5, v4&v6 are shorted in the application circuit as shown in the following f igure.
ST7065C v1.4c 2009/08/21 12/14 timing characteristics cl2 data in (dl1, dl2) (dr1, dr2) data out (dl1, dl2) (dr1, dr2) cl1 m v ih v il t r t wckh t f t wckl t dh t su t d v oh v ol t sl t ls t ls t wckh t r t su
ST7065C v1.4c 2009/08/21 13/14 d.c characteristics: symbol parameter test condition min. typ. max. unit applicable pin vdd operating voltage - 2.7 - 5.5 v - vlcd driver supply voltage vdd-vee 3 - 11 v - vih input high voltage - 0.7 vdd - vdd v vil input low voltage - 0 - 0.3 vdd v ilkg input leakage current vin = 0 ~ vdd -5 - 5 ua cl1,cl2,m,shl1,s hl2 dl1,dl2,dr1,dr2 voh output high voltage ioh = -0.4ma vdd -0.4 - - v vol output low voltage iol = +0.4ma - - 0.4 v dl1,dl2,dr1,dr2 v1~v6, s[1]~s[40] idd operating current fcl2 = 400khz - 100 300 ua vdd,vee iv leakage current vin = vdd ~ vee -10 - 10 ua v1 ~ v6 a.c characteristics: symbol parameter test condition min. max. unit applicable pin fcl data shift frequency - - 400 khz cl2 twckh clock high level width - 800 - ns cl1,cl2 twckl clock low level width - 800 - ns cl2 tsl clock set-up time cl2 cl1 500 - ns cl1,cl2 tls clock set-up time cl1 cl2 500 - ns cl1,cl2 tr/tf clock rise/fall time - - 200 ns cl1,cl2 tsu data set-up time - 300 - ns dl1,dl2,dr1,dr2 tdh data hold time - 300 - ns dl1,dl2,dr1,dr2 td data delay time cl = 15 pf - 500 ns dl1,dl2,dr1, dr2 maximum absolute ratings: symbol parameters min. max. unit vdd supply voltage -0.3 7 v topr operating temperature -20 85 tstg storage temperature -55 125
ST7065C v1.4c 2009/08/21 14/14 application circuit: (2line x 24word) st7066u ST7065C ST7065C dot matrix lcd panel -v or gnd vcc(+5v) regsister regsister regsister regsister regsister vr db0-db7 to mpu v5 v4 v3 v2 v1 m cl1 cl2 gnd vcc seg 1-40 com 1-16 vee vss shl2 shl1 fcs vdd dl1 v1 v2 v3 v4 v5 v6 v1 v2 v3 v4 v5 v6 vee vss shl2 shl1 fcs vdd dl1 m cl2 cl1 dr1 dl2 dr2 m cl2 cl1 dr1 dl2 dr2 seg 1-40 seg 1-40 note: regsister=2.2k~10k ohm vr=10k~30kohm d

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